`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    17:25:28 11/07/2012 
// Design Name: 
// Module Name:    LPF_ROM_CTR 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module ROM_CTR #(parameter LOG_LEN=8, LEN=129, WIDTH=16, OFFSET=0)
(
	input clk,
	input rst,
	input signed[WIDTH-1:0] in_data_r,
	input signed[WIDTH-1:0] in_data_i,
	output signed[WIDTH-1:0] out_data_r,
	output signed[WIDTH-1:0] out_data_i,
	output reg[LOG_LEN-1:0] out_addr
    );
	
	always@(posedge clk or negedge rst)
	if(!rst)
		out_addr <= 0;
	else if(out_addr == LEN-1)
		out_addr <= 0;
	else
		out_addr <= out_addr + 1;
	
	assign out_data_r = in_data_r;
	assign out_data_i = in_data_i;
	
endmodule
